The Cal Poly San Luis Obispo Computer Science department is hiring a tenure-track faculty position in HPC. Click here for a direct link to the position description. They have a shiny new lab for teaching and research in parallel computing, along with a fantastic student body that will certainly attract talented people for this position.Cal Poly San Luis Obispo is located … [Read more...]
More Trinity Racks Installed
"The proof of the pudding is in the tasting" is coming to fruition for the Trinity procurement as Cray installs more racks of the Trinity self-hosted Intel Knights Landing (KNL) processors. Each set of 12 cabinets is delivered, connected and tested one row at a time, by the Cray installation team. When all the phase-one cabinets have been delivered (60 in all), Cray will … [Read more...]
Intel Extends Barcelona Supercomputing Center
Intel extended it's research collaboration with the Barcelona Supercomputing Center (BSC) – one of four Intel exascale labs in Europe. Begun in 2011 and now extended to September 2017, the Intel-BSC work focuses on scalability issues as parallel applications move towards the exascale. BSC has been making HPC tools such as an instrumentation package (Extrae), a performance data … [Read more...]
Intel Xeon Phi Optimization Part 1 of 3: Multi-Threading and Parallel Reduction
This tutorial begins a 3-part series of educational publications on performance optimization in applications for Intel Xeon Phi coprocessors. In this publication, Ryo Asai (a Researcher at Colfax International) and Andrey Vladimirov (Head of HPC Research at Colfax International) will focus on some aspects of thread parallelism implementation in the OpenMP … [Read more...]
Port Some CUDA Codes To Intel Xeon Phi Simply and Efficiently
This tutorial shows that it relatively easy to port many CUDA C/C++ source codes to OpenMP. In the past, such efforts were not generally considered worthwhile because of the large performance difference between multicore processors (that use OpenMP) and GPUs. The introduction of teraflop/s Intel Xeon Phi coprocessors eliminated that performance difference, which makes it much … [Read more...]
GCC 5.1 Now Available – Includes Preliminary OpenACC and OpenMP 4.0
The GNU project has released GCC 5.1, which is a major update including a preliminary version of OpenACC and OpenMP 4.0 capability. The source code can be downloaded and built from the mirror sites or the SVN server. Don't expect much in terms of OpenACC performance as the execution model currently only allows for one gang, one worker, and a number of vectors. OpenMP 4 looks … [Read more...]
Rumor – US Bans Intel Xeon Phi Sales in China
In the unsubstantiated rumor but worth knowing if true category, VRworld reported that the US government has banned Intel Xeon Phi sales in China. Intel Xeon Phi is the current basis of the 33 PF/s Tianhe-2 supercomputer. … [Read more...]
Intel Xeon Phi Benefits Commercial Engineering Simulation Code
ANSYS and Intel worked closely together to optimize the first commercial engineering simulation package multi-core Intel® Xeon® processor E5-2600 v2 and v3 families and the many-core Intel® Xeon Phi™ coprocessor. Results indicate a 3.1x speedup after upgrading from a Xeon V2 to V3 solution, and a further 1.7x speedup when using an Intel® Xeon Phi™ 7120 coprocessor (or total … [Read more...]
First Trinity Testbed Hardware Delivered – Likely Running Knights Landing
The NNSA blog reports that the first Trinity test bed hardware has been delivered to both LANL and Sandia. Two systems were delivered to Los Alamos and one to Sandia. No word if any of these systems currently contain Knights Landing hardware, but it seems likely given that Trinity will run Knights Landing in self-hosted mode. Self-hosted systems eliminate concerns about data … [Read more...]
NP-Complete Parallel Thread Placement Addressed in Milliseconds via MIT “Best Paper” Heuristic
The problem of jointly allocating computations and data is a known NP-hard problem. A heuristic proposed by MIT researchers Nathan Beckmann, Po-An Tsai, and Daniel Sanchez recently the best-paper award at the IEEE Symposium on High-Performance Computer Architecture for a place-and-route algorithm that runs in milliseconds and finds a solution that is more than 99 percent as … [Read more...]