• Home
  • News
  • Tutorials
  • Analysis
  • About
  • Contact

TechEnablement

Education, Planning, Analysis, Code

  • CUDA
    • News
    • Tutorials
    • CUDA Study Guide
  • OpenACC
    • News
    • Tutorials
    • OpenACC Study Guide
  • Xeon Phi
    • News
    • Tutorials
    • Intel Xeon Phi Study Guide
  • OpenCL
    • News
    • Tutorials
    • OpenCL Study Guide
  • Web/Cloud
    • News
    • Tutorials
You are here: Home / Featured article / Justin Rattner To Give Keynote at SC15 Energy Efficient High Performance Computing Workshop

Justin Rattner To Give Keynote at SC15 Energy Efficient High Performance Computing Workshop

October 28, 2015 by Rob Farber Leave a Comment

Parallel Computing Pioneer and Former Intel Senior Fellow and Chief Technology Officer, Justin Rattner, to Deliver Keynote Address at 6th Annual Energy Efficient HPC Working Group Workshop at Supercomputing Conference, SC15

DATE:  Monday, November 16th

TIME: Workshop: 9:00AM – 5:30PM     Keynote:  2:00 PM

LOCATION: SC15, Austin Texas Hilton Salon A

The 6th annual event in the Energy Efficient High Performance Computing Workshop (EE HPC WG) series, the SC15 EE HPC WG Workshop, recognized internationally as an influential forum for accelerating HPC energy efficiency with a focus on integrating HPC systems with data center infrastructure, announced today that parallel supercomputing pioneer, former Intel Senior Fellow, Chief Technology Officer (CTO) and Vice President of Intel Corporation, Justin Rattner, will deliver the keynote address at the SC15 6th  Annual EE HPC WG Workshop on Monday, November 16th, 2015.

image1

Rattner was head of Intel Labs and in this role, directed Intel’s global research efforts in microprocessors, systems and communications including the company’s disruptive research activity.  “Justin’s vision and leadership in the late 80s and early 90s led to the first teraflop supercomputer and helped shape the technology direction and innovation that drove an exciting era of parallel supercomputing,” said Wilfred Pinfold, SC15 Steering Committee Member and Chief Executive Officer at Concurrent Systems LLC.  “He is uniquely qualified to talk about perspectives on HPC system architecture and energy efficiency: looking back and forward.”

“Intel first highlighted the then-projected exponential increase in chip power as far back as 2001 in a keynote address at the International Solid State Circuits Conference,” recalls retired Intel CTO, Justin Rattner. The “Surface of the Sun” slide from that talk went viral within the limit of the Internet at the time. Despite the dire warnings, it wasn’t until a next-generation Intel microprocessor was cancelled just short of production that the industry understood why power consumption had to be fully addressed at every level of design from the silicon manufacturing process to the application software design. In other words, from the atoms and bits to intelligent system management software, every aspect of energy efficiency had to be re-engineered to keep total power within the limits of the mechanical and electrical system design. The switch from desktop to laptop and from laptop to smartphone further upped the ante. For tomorrow’s exascale systems, the three biggest design challenges are power, power, and power.”

Rattner joined Intel in 1973 and was named its first Principal Engineer in 1979 and its fourth Intel Fellow in 1988.  In 1989, he was named Scientist of the Year by R&D Magazine for his leadership in parallel and distributed computer architecture.  In December 1996, Rattner was featured as Person of the Week by ABC World News for his visionary work on the Department of Energy ASCI Red System, the fastest computer in the world between 1996 and 2000.  In 1997, Rattner was honored as one of the Computing200, the 200 individuals having the greatest impact on the U.S. computer industry today, and subsequently profiled in the book Wizards and Their Wonders from ACM Press.

About SC15 EE HPC WG Workshop

“The EE HPC WG is a preeminent forum for major supercomputing centers to collaborate on best practices and recommendations for energy efficiency improvements and reducing operational costs,” said Dona Crawford, Associate Director of Computation at Lawrence Livermore National Laboratory. “The SC15 EE HPC WG workshop provides an excellent opportunity for EE HPC WG members to meet each other in person as well as a venue for non-members to find out more about the activities of the WG.”

The SC15 EE HPC WG workshop provides a strong blended focus that includes both the facilities and system perspectives; from architecture through design and implementation. The topics reflect the activities and interests of the EE HPC WG, which is a group with 600 members from more than 20 different countries. Registration for the workshop is via SC15 and can be done at http://sc15.supercomputing.org/register.

More information about the workshop can be found at: https://eehpcwg.llnl.gov/pages/conf_sc15.htm

 

Interested individuals can also contact:

Natalie Bates

Co-Chair, Energy Efficient HPC Working Group

Natalie.jean.bates@gmail.com

(253) 448-3186

10715 Guthrie Road

Anderson Island, WA 98303

Share this:

  • Twitter

Filed Under: Featured article, Featured news, News Tagged With: HPC

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Tell us you were here

Recent Posts

Farewell to a Familiar HPC Friend

May 27, 2020 By Rob Farber Leave a Comment

TechEnablement Blog Sunset or Sunrise?

February 12, 2020 By admin Leave a Comment

The cornerstone is laid – NVIDIA acquires ARM

September 13, 2020 By Rob Farber Leave a Comment

Third-Party Use Cases Illustrate the Success of CPU-based Visualization

April 14, 2018 By admin Leave a Comment

More Tutorials

Learn how to program IBM’s ‘Deep-Learning’ SyNAPSE chip

February 5, 2016 By Rob Farber Leave a Comment

Free Intermediate-Level Deep-Learning Course by Google

January 27, 2016 By Rob Farber Leave a Comment

Intel tutorial shows how to view OpenCL assembly code

January 25, 2016 By Rob Farber Leave a Comment

More Posts from this Category

Top Posts & Pages

  • ARM64 with CUDA Early Access Boards Now Available
  • Altera OpenCL Programmable FPGA Talks QPI, HMC, and 100G Optical Interconnect
  • N-body Methods on Intel Xeon Phi Coprocessors
  • Performance Optimization Of Black-Scholes Pricing On Intel Xeon Phi
  • Turn Glasses or Sunglasses into Smart Glasses with Sony Device

Archives

© 2026 · techenablement.com