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You are here: Home / Archives for Intel

Morton Order Improves Performance

November 11, 2014 by Rob Farber Leave a Comment

Author Kerry Evans writes in his High Performance Parallelism Pearls  chapter, "There are many facets to performance optimization but three issues to deal with right from the beginning are memory access, vectorization, and parallelization. Unless we can optimize these, we cannot achieve peak performance.” Specifically, this chapter examines a method of mapping multidimensional … [Read more...]

Sparse matrix-vector multiplication: parallelization and vectorization

November 10, 2014 by Rob Farber Leave a Comment

The chapter authors (Albert-Jan N. Yzelman, Dirk Roose, and Karl Meerbergen) note that, "Current hardware trends lead to an increasing width of vector units as well as to decreasing effective bandwidth-per-core. For sparse computations these two trends conflict.”  For this reason they designed a usable and efficient data structure for vectorized sparse computations  on … [Read more...]

Scalable Out-Of-Core Solvers On A Cluster

November 7, 2014 by Rob Farber Leave a Comment

This chapters documents the implementation of a parallel distributed memory out-of-core (OOC) solver for performing LU and Cholesky factorizations of a large dense matrix on clusters equipped with Intel Xeon Phi coprocessors. The code was ported from CUDA with high-level library routines in CUBLAS This matches well with the offload model for the coprocessor using the … [Read more...]

Heterogeneous MPI Optimization With ITAC

November 6, 2014 by Rob Farber Leave a Comment

This chapter focuses on the workload balance of MPI applications running in heterogeneous cluster environment consisting of Intel Xeon processors and Intel Xeon Phi coprocessors in a financial industry application that calculates Asian option payoffs. Three cases are considered: unbalanced symmetric MPI code, manual balancing with pre-calculated performances of the cluster … [Read more...]

Profiling Guided Optimization On Intel Xeon Phi

November 5, 2014 by Rob Farber Leave a Comment

This chapter in High Performance Parallelism Pearls by Andrey Vladimirov focuses on the use of Intel VTune Amplifier XE reports to understand where to apply optimization on matrix transposition, a small and self-contained workload of great practical value. The optimization process applied to the code relies exclusively on programming in a high-level language plus utilization of … [Read more...]

Characterization And Optimization Methodology Applied To Stencil Computations

November 4, 2014 by Rob Farber Leave a Comment

The  chapter discuss characterization and optimization methodology applied to a 3D finite differences (3DFD) algorithm used to solve constant or variable density isotropic acoustic wave equation (Iso3DFD). From an unoptimized version to the most optimized, the authors achieved a six-fold performance improvement on Intel Xeon E5-2697v2 processors and a nearly thirty-fold … [Read more...]

Portable Performance with OpenCL On Intel Xeon Phi

November 3, 2014 by Rob Farber Leave a Comment

This High Performance Parallelism Pearl show the potential for using the OpenCL™ standard parallel programming language to deliver portable performance on Intel Xeon Phi coprocessors, Xeon processors, and many-core devices such as GPUs from multiple vendors. This portable performance can be delivered from a single program without needing multiple versions of the code, an … [Read more...]

High Performance Ray Tracing With Embree On Intel Xeon Phi

October 31, 2014 by Rob Farber Leave a Comment

Ray tracing is a technique for generating images of synthetic scenes. Because ray tracing simulates the physics of light transport in the real world, it can be used to achieve high quality and even photorealistic results. The chapter authors in High Performance Parallelism Pearls describe how the Intel Embree ray tracing kernel library can be used to achieve high performance … [Read more...]

Data Transfer Using The Intel COI Library

October 30, 2014 by Rob Farber Leave a Comment

This short chapter gives an introduction to the Intel COI library and discusses the pros and cons of different data buffers as well as provides benchmarks on transfer latency and bandwidth between the host and the coprocessor. For any non-trivial applications, there is likely going to be a need to share data between the host and the coprocessor. These valuable information are … [Read more...]

Register For Lustre’s Brent Gorda Parallel Storage and Big Data HP-Cast

October 29, 2014 by Rob Farber Leave a Comment

Register here to join Brent Gorda, GM of Intel Corporations High Performance Data division as he presents on the topic of how the Intel® Enterprise Edition for Lustre* software makes parallel storage simpler to manage and more productive for data intensive applications. Big Data has been synonymous with high performance computing for decades, and has become the primary driver … [Read more...]

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