A teraflop/s computational capability is useless without data. The Intel Xeon Phi family supports a number of file systems including Lustre, NFS, Fraunhofer BeeGFS® (formerly FHGFS), and the Panasas® PanFS® file system. The chapter author, Michael Hebenstreit, also discusses the importance of a correct network setup. He notes in his chapter summary (courtesy Morgan … [Read more...]
Integrating Intel Xeon Phi Coprocessors into a Cluster Environment
The chapter authors build on the standard Intel MPSS documentation that provides the information required for workstation installs, but does not provide techniques needed for successful deployment in a cluster environment. Based on multiple authors' many years of experience managing HPC clusters and specific experience with the Intel Xeon Phi coprocessor family since the … [Read more...]
Power Analysis on the Intel Xeon Phi Coprocessor
Power has become the limiting factor today on how far we can scale an HPC cluster today. Some cluster installations today are running upwards of 20,000,000 watts (20MW) of power to solve large HPC applications. Power has now taken center-stage as a key challenge we need to address in order to scale a cluster to new levels of high performance. The chapter author, Claude J. … [Read more...]
Heterogeneous Computing with MPI On Intel Xeon Phi
The chapter authors discuss the hardware heterogeneity found in modern clusters and then analyze a typical Intel Xeon Phi coprocessor accelerated node on the Stampede cluster at TACC, with an eye towards how MPI is used in similar clusters, and the positioning an MPI task within the node. The performance through different communication pathways is highlighted using micro … [Read more...]
Concurrent Kernel Offloading On Intel Xeon Phi
Chapter 12 of High Performance Parallelism Pearls discusses optimizing performance when offloading concurrent kernels (e.g. task-parallelism) to the Intel Xeon Phi coprocessor. The authors state, "Our ultimate optimization target in this chapter is to improve the computational throughput of multiple small-scale workloads on the Intel Xeon Phi coprocessor by concurrent kernel … [Read more...]
Dynamic Load Balancing using OpenMP 4.0
Gilles Civario and Michael Lysaght from ICHEC show how to take advantage of the OpenMP 4.0 standard on Xeon and Intel Xeon Phi coprocessors to portably and efficiently maximize an N-body kernel on the entire available hardware. The chapter authors point out that the sample code can be used as a template applicable for countless of real live codes. By adapting this template to … [Read more...]
Free Colfax Intensive Intel Xeon Phi Training Slides
Colfax International is making the 280 page slide deck by Andrey Vladimirov and Vadim Karpusenko titled "Parallel Programming and Optimization with Intel Xeon Phi Coprocessors" available free to those who wish to register at this URL. This training is an intensive course for developers wishing to leverage the Intel MIC architecture. and increase their knowledge of multi-core … [Read more...]
N-body Methods on Intel Xeon Phi Coprocessors
The chapter authors (Rio Yokota and Mustafa Abdul Jabbar) achieve roughly 1.5 TF/s single-precision performance when running an optimized direct N-body kernel on an Intel Xeon Phi coprocessor. This level of performance was achieved through the use of OpenMP, SIMD directives, and _mm512 intrinsics. The authors note the strong scalability of the execution was close to ideal, … [Read more...]
A Many-Core Implementation Of The Direct N-body Problem
Chapter 9 of High Performance Parallelism Pearls presents several optimizations that are usually necessary to obtain good performance on an Intel Xeon Phi coprocessor that include: introducing a softening factor, exploring the impact of single- vs. double-precision, Improving tililing, utilizing an SoA (Structure of Arrays) layout, generating code that does not maintain IEEE … [Read more...]
Optimizing Gather/Scatter Patterns On Intel Xeon Phi
Many modern microarchitectures rely on single-instruction multiple-data (SIMD) execution to provide high compute capabilities in an energy efficient manner. Such microarchitectures including those employed by the most recent Intel Xeon processors and Intel Xeon Phi coprocessors are optimized and/or better suited to dealing with contiguous loads and stores than non-contiguous … [Read more...]