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You are here: Home / News / Intel SPMD Compiler (ISPC) for Xeon and Xeon Phi

Intel SPMD Compiler (ISPC) for Xeon and Xeon Phi

August 25, 2014 by Rob Farber Leave a Comment

When #pragma SIMD is not enough, companies and projects such as Intel, Embree,  Dreamworks, Pixar, Autodesk, and SURFsara are looking to the freely available Intel SPMD Program Compiler (ispc) to achieve high vector performance on Xeon and Intel Xeon Phi devices.  ISPC is  LLVM-based and designed to exploit Intel SIMD architectures from mobile to HPC. A key concept behind ispc is to make vector types explicit rather than having them be discovered by the compiler, which eliminates the uncertainty when specifying pragmas and then reading vector reports to see if the compiler did what it should have done. Basically “uniform” and “variable” type modifiers are added via a C-based syntax so the code looks sequential but executes in parallel (SPMD). This means programmers can easily mix scalar and vector computation. Speedups per core of 3x or more are claimed to be regularly observed on CPUs with 4-wide vector SSE units and 5x-6x on CPUs with 8-wide AVX vector units – all without any of the difficulty of writing intrinsics code. 

For more information:

  • Siggraph 2014, “Writing Efficient IA Vector Code using ISPC“
  • https://ispc.github.io/
  • INPAR 2012 paper, “ispc: A SPMD Compiler for High-Performance CPU Programming“
  • The Google  ispc-users forum
  • Compiling for the Intel Xeon Phi Architecture

 

 

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Filed Under: Featured news, News, News, Xeon Phi Tagged With: HPC, Intel, Intel Xeon Phi

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