Chapter 9 of High Performance Parallelism Pearls presents several optimizations that are usually necessary to obtain good performance on an Intel Xeon Phi coprocessor that include: introducing a softening factor, exploring the impact of single- vs. double-precision, Improving tililing, utilizing an SoA (Structure of Arrays) layout, generating code that does not maintain IEEE precision, and the use of dynamic OpenMP scheduling to account for cache misses. It also explains why these optimizations where done intending that the applicability of the chapter is broader than the N-Body kernel that is used to drive the presentation.
Unique to this chapter, the authors discussed how to quickly find a target for the optimization process and demonstrated that the final optimized version of the code obtained an 89% of the upper bound performance. They noted that efforts to optimize for the Intel Xeon Phi coprocessor also had a positive effect on the performance of the identical code when running on an Intel Xeon processor.
Chapter Authors
Alejandro Duran
Alejandro Duran has been an Application Engineer for Intel Corporation for the last two years. Previously, Alex was a senior researcher in the Barcelona Supercomputing Center. He holds a PhD from the Polytechnic University of Catalonia. He has been part of the OpenMP Language committee for the past 9 years.
Larry Meadows
Larry Meadows has worked on compilers, tools, and applications software for HPC since 1982. He was a founding member of The Portland Group and has been working for Intel Corporation in Oregon for the last ten years.
Click to see the overview article “Teaching The World About Intel Xeon Phi” that contains a list of TechEnablement links about why each chapter is considered a “Parallelism Pearl” plus information about the chapter author(s).
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