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You are here: Home / Featured article / Native File Systems on Intel Xeon Phi

Native File Systems on Intel Xeon Phi

October 24, 2014 by Rob Farber Leave a Comment

A teraflop/s computational capability is useless without data. The Intel Xeon Phi family supports a number of file systems including Lustre, NFS, Fraunhofer BeeGFS® (formerly FHGFS), and the Panasas® PanFS® file system. The chapter author, Michael Hebenstreit, also discusses the importance of a correct network setup. He notes in his chapter summary (courtesy Morgan Kaufmann):

This chapter provided the necessary information to create a cluster where Intel Xeon Phi coprocessors can be addressed as standard independent nodes in the network topology. Both network configuration and cluster file systems need to be addressed. With those components in place, utilizing distributed MPI programs running on the coprocessor can be as easy as recompiling them using the steps provided in this chapters’  introduction – though optimizing the programs to account for the specific computational capabilities and differences between processors and coprocessors in the cluster will still be another step.

Cover3D-fs8For more information:

  •  The Colfax report, “File I/O on Intel Xeon Phi Coprocessors: RAM disks, VirtIO, NFS and Lustre“
  •  NFS:
    • http://en.wikipedia.org/wiki/Network_File_System
  • Lustre:
    • http://wiki.lustre.org/index.php/Main_Page
    • http://www.intel.com/content/www/us/en/software/intel-­solutions‐for-­lustre-­software.html
  • Panasas:
    • http://www.panasas.com/
  • BeeGFS:
    • http://www.fhgfs.com/cms/

Chapter Author

Michael Hebenstreit

Michael Hebenstreit

Michael Hebenstreit (michael.hebenstreit@intel.com) is a senior cluster architect and tech lead for the Endeavor HPC benchmarking datacenter with over 25 years’ experience in HPC. In his 9 years at Intel he helped to make Endeavor a prime HPC benchmarking datacenter in the world and was essential in integrating the Intel® Xeon Phi™ coprocessors into the cluster.

Click to see the overview article “Teaching The World About Intel Xeon Phi” that contains a list of TechEnablement links about why each chapter is considered a “Parallelism Pearl” plus information about James Reinders and Jim Jeffers, the editors of High Performance Parallelism Pearls.

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Filed Under: Featured article, Featured news, News, News, Xeon Phi Tagged With: HPC, Intel, Intel Xeon Phi, x86

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