• Home
  • News
  • Tutorials
  • Analysis
  • About
  • Contact

TechEnablement

Education, Planning, Analysis, Code

  • CUDA
    • News
    • Tutorials
    • CUDA Study Guide
  • OpenACC
    • News
    • Tutorials
    • OpenACC Study Guide
  • Xeon Phi
    • News
    • Tutorials
    • Intel Xeon Phi Study Guide
  • OpenCL
    • News
    • Tutorials
    • OpenCL Study Guide
  • Web/Cloud
    • News
    • Tutorials
You are here: Home / Featured article / GCC 5.1 Now Available – Includes Preliminary OpenACC and OpenMP 4.0

GCC 5.1 Now Available – Includes Preliminary OpenACC and OpenMP 4.0

April 26, 2015 by Rob Farber Leave a Comment

The GNU project has released GCC 5.1, which is a major update including a preliminary version of OpenACC and OpenMP 4.0 capability. The source code can be downloaded and built from the mirror sites or the SVN server.

Don’t expect much in terms of OpenACC performance as the execution model currently only allows for one gang, one worker, and a number of vectors. OpenMP 4 looks interesting and includes offload capabilities.

New Languages and Language specific improvements

  • OpenMP 4.0 specification offloading features are now supported by the C, C++, and Fortran compilers. Generic changes:
    • Infrastructure (suitable for any vendor).
    • Testsuite which covers offloading from the OpenMP 4.0 Examples document.

    Specific for upcoming Intel Xeon Phi products:

    • Run-time library.
    • Card emulator.
  • GCC 5 includes a preliminary implementation of the OpenACC 2.0a specification.  See the OpenACC wiki page for more information.

It’s actually quite easy to build gcc from source. Give it a try!

Note!

  • Rebuild all your C++ source code per RedHat.
  • New ISA extensions support AVX-512{BW,DQ,VL,IFMA,VBMI} of Intel’s CPU codenamed Skylake Server was added to GCC including inline assembly support, new intrinsics, and basic autovectorization. These new AVX-512 extensions are available via the following GCC switches: AVX-512 Vector Length EVEX feature: -mavx512vl, AVX-512 Byte and Word instructions: -mavx512bw, AVX-512 Dword and Qword instructions: -mavx512dq, AVX-512 FMA-52 instructions: -mavx512ifmaand for AVX-512 Vector Bit Manipulation Instructions: -mavx512vbmi.

Share this:

  • Twitter

Filed Under: Featured article, Featured news, News, News, News, openacc, Xeon Phi Tagged With: OpenACC OpenMP4

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Tell us you were here

Recent Posts

Farewell to a Familiar HPC Friend

May 27, 2020 By Rob Farber Leave a Comment

TechEnablement Blog Sunset or Sunrise?

February 12, 2020 By admin Leave a Comment

The cornerstone is laid – NVIDIA acquires ARM

September 13, 2020 By Rob Farber Leave a Comment

Third-Party Use Cases Illustrate the Success of CPU-based Visualization

April 14, 2018 By admin Leave a Comment

More Tutorials

Learn how to program IBM’s ‘Deep-Learning’ SyNAPSE chip

February 5, 2016 By Rob Farber Leave a Comment

Free Intermediate-Level Deep-Learning Course by Google

January 27, 2016 By Rob Farber Leave a Comment

Intel tutorial shows how to view OpenCL assembly code

January 25, 2016 By Rob Farber Leave a Comment

More Posts from this Category

Top Posts & Pages

  • High Performance Ray Tracing With Embree On Intel Xeon Phi
  • MultiOS Gaming, Media, and OpenCL Using XenGT Virtual Machines On Shared Intel GPUs
  • Intel Xeon Phi Study Guide
  • Free Intermediate-Level Deep-Learning Course by Google

Archives

© 2025 · techenablement.com