Antonio Valles and Weiqun Zhang note the optimizations discussed in their High Performance Parallelism Pearls chapter that, “significantly improved concurrency on both Intel Xeon Phi coprocessors and Intel Xeon processors” by transforming a fine-grain thread parallel approach to a more coarse-grain, memory allocation considerate approach plus improving vectorization. They observe that many applications are not properly optimized to take advantage of so many hybrid (MPI + OpenMP) hardware threads per node. In addition, their chapter briefly demonstrates how new features in VTune Amplifier XE are used for OpenMP analysis on the LBNL minimalist SMC combustion code that acts as a computational proxy for the full version that solves the multicomponent, reacting, compressible Navier-‐Stokes equations.
Specifically, the chapter code optimizations start with the adoption of a coarse-grained OpenMP approach (referred to as a ThreadBox) followed by two optimizations (stack allocation and blocking) to account for side-effects plus an additional form of optimization that restructured loops for SIMD vectorization in Fortran.
SMC Simulation (courtesy Morgan Kaufmann)
Chapter Authors
Weiqun Zhang
Weiqun Zhang is a member of the Center for Computational Sciences and Engineering at Lawrence Berkeley National Laboratory. He received his B.S. in physics from the University of Science and Technology in China, and his Ph.D. in astronomy and astrophysics from the University of California, Santa Cruz. His research interests lie in high-performance computing, numerical methods for partial differential equations, and applications to science and engineering fields including combustion and astrophysics.
Antonio Valles
Antonio Valles is Senior Software Engineer at Intel Corporation currently focused on performance analysis and optimizations for the Intel Xeon Phi coprocessors. Antonio has analyzed and optimized software at Intel since 1997 spanning client, mobile, and HPC segments. Antonio loves to code and has written multiple internal post-Si and pre-Si tools to help analyze and optimize applications. He received his BS in Electrical Engineering at Arizona State University in 1997.
Click to see the overview article “Teaching The World About Intel Xeon Phi” that contains a list of TechEnablement links about why each chapter is considered a “Parallelism Pearl” plus information about James Reinders and Jim Jeffers, the editors of High Performance Parallelism Pearls.
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