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You are here: Home / Archives for Rob Farber

N-body Methods on Intel Xeon Phi Coprocessors

October 16, 2014 by Rob Farber Leave a Comment

The chapter authors (Rio Yokota and Mustafa Abdul Jabbar) achieve roughly 1.5 TF/s single-precision performance when running an optimized direct N-body kernel on an Intel Xeon Phi coprocessor. This level of performance was achieved through the use of OpenMP, SIMD directives, and _mm512 intrinsics. The authors note the strong scalability of the execution was close to ideal, … [Read more...]

A Many-Core Implementation Of The Direct N-body Problem

October 15, 2014 by Rob Farber Leave a Comment

Chapter 9 of High Performance Parallelism Pearls presents several optimizations that are usually necessary to obtain good performance on an Intel Xeon Phi coprocessor that include: introducing a softening factor, exploring the impact of single- vs. double-precision, Improving tililing, utilizing an SoA (Structure of Arrays) layout, generating code that does not maintain IEEE … [Read more...]

Optimizing Gather/Scatter Patterns On Intel Xeon Phi

October 14, 2014 by Rob Farber Leave a Comment

Many modern microarchitectures rely on single-instruction multiple-data (SIMD) execution to provide high compute capabilities in an energy efficient manner. Such microarchitectures including those employed by the most recent Intel Xeon processors and Intel Xeon Phi coprocessors are optimized and/or better suited to dealing with contiguous loads and stores than non-contiguous … [Read more...]

Deep-­Learning And Numerical Optimization

October 13, 2014 by Rob Farber Leave a Comment

The massively parallel mapping and code described in this chapter is generic and can be applied to a broad spectrum of numerical optimization and machine-learning algorithms ranging from neural networks to support vector machines to expectation maximization and independent components analysis. Many of these techniques are heavily used in lucrative data-mining and social media … [Read more...]

Seattle LibreFest Oct. 26 2014 In-Person And Via IRC

October 12, 2014 by Rob Farber Leave a Comment

Representatives of the LibreOffice QA and Developer Teams will be on hand at the UW Communications Building, Rm 242, Seattle, WA to teach interested users how to get involved with the LibreOffice community. They will be providing food and t-shirts for all LibreFest participants, so grab your laptop, roll up your sleeves, and  dig in! Can't make it to Seattle?  ... then  join … [Read more...]

HTML5 Progress – Confirmed Netflix Works With Chrome And Ubuntu 14.04LTS

October 11, 2014 by Rob Farber Leave a Comment

Ubuntu 14.04 users can now simply load Netflix and start viewing - no beta builds, wine emulation or other work-arounds. Hopefully other services like Amazon Instant Video will follow suite. … [Read more...]

Intel Xeon Phi Provides Cambridge 30x Speedup in Production COSMOS WALLS Code

October 10, 2014 by Rob Farber Leave a Comment

Professor Paul Shellard, the COSMOS Director at Cambridge University reports a 30x speedup of the heavily utilized production WALLS code and he notes "Our expectation is that all our cosmological field theory codes, like WALLS, will have similarly large speed-ups when optimized and ported to Xeon Phi."  Currently the project is transferring a larger portion of the CMB analysis … [Read more...]

Parallel Evaluation Of Fault Tree Expressions

October 10, 2014 by Rob Farber Leave a Comment

Readers are guided through a progression from a scalar fault tree code to one mapped effectively to Intel Xeon Phi with the open-source ispc (Intel SPMD Program Compiler). Fault trees express failure relationships between systems using Boolean logic to evaluate the vulnerability of systems based on component reliability, system redundancy, physical protection, and other — … [Read more...]

Plesiochronous (Loosely Synchronous) Phasing Barriers To Avoid Thread Inefficiencies

October 9, 2014 by Rob Farber Leave a Comment

Jim Dempsey bests expert Intel programmers by 40% - 50% simply by using a little bit of ingenuity, along with a slightly different programming technique. He notes that, "a substantial portion of previously lost thread barrier wait time" can be recovered simply by using loosely synchronous (plesiochronous) barriers instead of strictly synchronous barriers.  Jim points out that, … [Read more...]

Micron Automata Processor SDK Now Available – Includes Online Demo!

October 8, 2014 by Rob Farber Leave a Comment

Click here to try a web-enabled intro simulation or visit micronautomata.com to sign up for a full preview of the Micron Automata Processor SDK (Software Development Kit) that includes a visual development environment, compiler, design rules checker, regular expression to automata generator and AP simulator. The SDK is also available through membership with the Center for … [Read more...]

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