Chapter 12 of High Performance Parallelism Pearls discusses optimizing performance when offloading concurrent kernels (e.g. task-parallelism) to the Intel Xeon Phi coprocessor. The authors state, "Our ultimate optimization target in this chapter is to improve the computational throughput of multiple small-scale workloads on the Intel Xeon Phi coprocessor by concurrent kernel … [Read more...]
Dynamic Load Balancing using OpenMP 4.0
Gilles Civario and Michael Lysaght from ICHEC show how to take advantage of the OpenMP 4.0 standard on Xeon and Intel Xeon Phi coprocessors to portably and efficiently maximize an N-body kernel on the entire available hardware. The chapter authors point out that the sample code can be used as a template applicable for countless of real live codes. By adapting this template to … [Read more...]
Free Colfax Intensive Intel Xeon Phi Training Slides
Colfax International is making the 280 page slide deck by Andrey Vladimirov and Vadim Karpusenko titled "Parallel Programming and Optimization with Intel Xeon Phi Coprocessors" available free to those who wish to register at this URL. This training is an intensive course for developers wishing to leverage the Intel MIC architecture. and increase their knowledge of multi-core … [Read more...]
N-body Methods on Intel Xeon Phi Coprocessors
The chapter authors (Rio Yokota and Mustafa Abdul Jabbar) achieve roughly 1.5 TF/s single-precision performance when running an optimized direct N-body kernel on an Intel Xeon Phi coprocessor. This level of performance was achieved through the use of OpenMP, SIMD directives, and _mm512 intrinsics. The authors note the strong scalability of the execution was close to ideal, … [Read more...]
A Many-Core Implementation Of The Direct N-body Problem
Chapter 9 of High Performance Parallelism Pearls presents several optimizations that are usually necessary to obtain good performance on an Intel Xeon Phi coprocessor that include: introducing a softening factor, exploring the impact of single- vs. double-precision, Improving tililing, utilizing an SoA (Structure of Arrays) layout, generating code that does not maintain IEEE … [Read more...]
Optimizing Gather/Scatter Patterns On Intel Xeon Phi
Many modern microarchitectures rely on single-instruction multiple-data (SIMD) execution to provide high compute capabilities in an energy efficient manner. Such microarchitectures including those employed by the most recent Intel Xeon processors and Intel Xeon Phi coprocessors are optimized and/or better suited to dealing with contiguous loads and stores than non-contiguous … [Read more...]
Deep-Learning And Numerical Optimization
The massively parallel mapping and code described in this chapter is generic and can be applied to a broad spectrum of numerical optimization and machine-learning algorithms ranging from neural networks to support vector machines to expectation maximization and independent components analysis. Many of these techniques are heavily used in lucrative data-mining and social media … [Read more...]
Intel Xeon Phi Provides Cambridge 30x Speedup in Production COSMOS WALLS Code
Professor Paul Shellard, the COSMOS Director at Cambridge University reports a 30x speedup of the heavily utilized production WALLS code and he notes "Our expectation is that all our cosmological field theory codes, like WALLS, will have similarly large speed-ups when optimized and ported to Xeon Phi." Currently the project is transferring a larger portion of the CMB analysis … [Read more...]
Parallel Evaluation Of Fault Tree Expressions
Readers are guided through a progression from a scalar fault tree code to one mapped effectively to Intel Xeon Phi with the open-source ispc (Intel SPMD Program Compiler). Fault trees express failure relationships between systems using Boolean logic to evaluate the vulnerability of systems based on component reliability, system redundancy, physical protection, and other — … [Read more...]
Plesiochronous (Loosely Synchronous) Phasing Barriers To Avoid Thread Inefficiencies
Jim Dempsey bests expert Intel programmers by 40% - 50% simply by using a little bit of ingenuity, along with a slightly different programming technique. He notes that, "a substantial portion of previously lost thread barrier wait time" can be recovered simply by using loosely synchronous (plesiochronous) barriers instead of strictly synchronous barriers. Jim points out that, … [Read more...]