Poetically noting that “a rising tide lifts all boats”, authors Guillaume Colin de Verdière and Jason D. Sewall demonstrate a 12x increase on Intel Xeon Phi and over 5x increase on Intel Xeon using, “a common set of optimizations [that] benefit both general-purpose Xeon processors and more specialized Xeon Phi accelerators” in chapter 2 of High Performance Parallelism Pearls. A huge number of scientific codes that are used everyday are running slowly on modern hardware due to a number of factors, but software/programming model inertia and increasing single-node parallelism are chief among them. To assist the reader, the authors examine a real-world shock hydrodynamics code to show that great improvements in performance can be achieved though simple models of hardware and computation such as arithmetic efficiency, instruction-level parallelism, and data-parallelism.
The subject of the chapter case study is a modest-sized yet real-world code called Hydro2D, that is developed in CEA (Commissariat à l’énergie atomique et aux énergies alternatives), a French governmental agency that performs both civilian and military research and development. The reference Hydro2D implementation is about 5000 lines of C/C++ that solves “shock hydrodynamics” problems; essentially, high-energy gas motion in two dimensions. In addition to its applicability to astrodynamics, the techniques in the code are very similar to that used in the astronautics community.
Godunov’s method which is part of the analysis was developed in 1959 by the Soviet mathematician S. K. Godunov. Hydro2D is a shock-capturing code that uses Godunov’s method to compute more accurate solutions to initial boundary-value problems (IBVP) .
Guillaume has been a CEA staff member since 1985. After being involved in large scientific codes’ developments, his focus went to high performance visualization and from there to the experimentation of GPU in the context of HPC. His current activity is to investigate the impact of new emerging technologies such as many-core onto legacy codes in the perspective of building an exascale system in the 2020 time frame.
Jason has been with Intel since 2010; he is a researcher in the MIC On Ramp Organization in the Data Center Group. He received undergraduate degrees in Mathematics and Computer Science from the University of Maine and his Ph.D. and M.S. in Computer Science from the University of North Carolina at Chapel Hill. Jason has published over 20 peer-reviewed research papers on a variety of topics, including graphics, physically-based modelling, parallel and high-performance computing, databases, computational finance, and graph algorithms.
Click to see the overview article “Teaching The World About Intel Xeon Phi” that contains a list of TechEnablement links about why each chapter is considered a “Parallelism Pearl” plus information about James Reinders and Jim Jeffers, the editors of High Performance Parallelism Pearls.