By utilizing the strengths of the Intel Xeon Phi coprocessor, the chapter 3 High Performance Parallelism Pearls authors were able to improve and modernize their code and "achieve great scaling, vectorization, bandwidth utilization and performance/watt". The authors (Jacob Weismann Poulsen, Karthik Raman and Per Berg) note, "The thinking process and techniques used in this … [Read more...]
From ‘Correct’ to ‘Correct & Efficient’: a Hydro2D case study with Godunov’s scheme
Poetically noting that "a rising tide lifts all boats", authors Guillaume Colin de Verdière and Jason D. Sewall demonstrate a 12x increase on Intel Xeon Phi and over 5x increase on Intel Xeon using, "a common set of optimizations [that] benefit both general-purpose Xeon processors and more specialized Xeon Phi accelerators" in chapter 2 of High Performance Parallelism … [Read more...]
The Unabridged Chapter 1 Introduction To High Performance Parallelism Pearls
Following is the full, unabridged text of the chapter 1 introduction (written by James Reinders) to High Performance Parallelism Pearls. Thanks to Morgan Kaufmann, James Reinders, and Jim Jeffers for giving permission so TechEnablment can make this available. After reading what James wrote, you will see that summarizing the introduction would simply have left out too much … [Read more...]
Teaching The World About Intel Xeon Phi
The newest book by James Reinders and Jim Jeffers, “High Performance Parallelism Pearls” distills the experience of sixty-nine HPC experts into twenty-eight chapters designed to teach the world about the performance capabilities of the massively-parallel Intel® Xeon Phi™ family of products. Source code for numerous working examples selected for their educational content, … [Read more...]
Latest Intel SDE Emulates New ISA Instructions For Knights Landing
Intel has released a new version of the Intel SDE (Software Development Emulator) so that customers can start working with upcoming instruction set extensions like AVX-512 for Knights Landing. The SDE can be downloaded after accepting a user agreement and used on Windows, Linux, and OS. It can also be used with the GNU gcc. The current version is 7.2 released on July 29, … [Read more...]
FabricEngine Leverages Python and LLVM For Digital Content Creation Everywhere
A company called FabricEngine (http://fabricengine.com) is leveraging the power of LLVM and Python to compile optimized code for Digital Content Creation (DCC) that can run on multicore and GPUs. Products like these demonstrate the acceptance of Python and LLVM into commercial/enterprise high-performance HPC applications just like PyFR and deep-learning. Integrated with … [Read more...]
GCC 5.0 Provides Full Cilk Plus Support
GNU has announced that GCC 5.0 will provide full support for Cilk Plus. Cilk Plus is an extension to the C and C++ languages to support data and task parallelism on multi-core, vector and Intel Xeon Phi coprocessors.It is reputed to be quite efficient and looks to be easy to use. The Intel icc compiler has supported Cilk Plus for years. GNU support now makes Cilk Plus available … [Read more...]
Accelerating the Traveling Salesman Problem with GPUs and Intel Xeon Phi
The traveling salesman problem (TSP) is an important computer science optimization problem with numerous real-world applications. There is a huge body of literature on TSP solutions. Following are a few GPU and Intel Xeon Phi accelerated solutions. TSPgpu TSPGPU v2.1 is a GPU-accelerated heuristic solver for the symmetric Traveling Salesman Problem with up to 32767 … [Read more...]
Intel Paper Detailing the Gen 7.5 GPU Architecture – Attention OpenCL Programmers !
Intel has labeled the Haswell graphic core as Gen 7.5 and the Ivy Bridge GPU as Gen.7. The latest Gen 7.5 Architecture paper, "The Compute Architecture of Intel® Processor Graphics Gen7.5" has now been released by Intel. This paper is written for those who wish to know the "architecture characteristics relevant to running compute applications on Intel® Processor … [Read more...]
Open Call to Run on the Beacon Intel Xeon Phi System
The National Institute for Computational Sciences (NICS) at the University of Tennessee (UT) is pleased to announce the 2014 open call for participation in the Beacon Project, an ongoing research project funded by the National Science Foundation and UT to explore the impact of emerging computer architectures on computational science and engineering. Beacon is a Cray CS300-AC … [Read more...]