• Home
  • News
  • Tutorials
  • Analysis
  • About
  • Contact

TechEnablement

Education, Planning, Analysis, Code

  • CUDA
    • News
    • Tutorials
    • CUDA Study Guide
  • OpenACC
    • News
    • Tutorials
    • OpenACC Study Guide
  • Xeon Phi
    • News
    • Tutorials
    • Intel Xeon Phi Study Guide
  • OpenCL
    • News
    • Tutorials
    • OpenCL Study Guide
  • Web/Cloud
    • News
    • Tutorials
You are here: Home / Featured article / Preparing For Knights Landing – Stay in HBM Memory

Preparing For Knights Landing – Stay in HBM Memory

February 9, 2015 by Rob Farber Leave a Comment

NERSC published an informative preparatory article for programming the forthcoming Cori supercomputer that notes each Intel Xeon Phi “Knight’s Landing” (KNL) devices will be running in a “self-hosted” mode, meaning that there will be no host/traditional processor. Everything – including the operating system – will run on KNL. This eliminates concerns about data movement as there is no “offload” mode, but the article notes that performance will be determined by the performance of the memory subsystem that holds the data and expressing enough fine-grained parallelism to keep the 60+ KNL cores busy.

Intel notes that the KNL memory system will utilize up to 16 GB of “on-package” or “High Bandwidth Memory” (HBM), which is claimed to have 5x the bandwidth of DDR4 memory (see slide below). It is very likely that many currently memory bandwidth bound applications KNC will see a large performance improvement on KNL purely as a result of HBM memory. Any data that does not fit into the HBM will need to be fetched from traditional DRAM and likely incur a greater than 5x performance penalty.

(Source Intel Corp)

(Source Intel Corp)

 

Share this:

  • Twitter

Filed Under: Featured article, Featured news, News, News, Xeon Phi Tagged With: Intel Xeon Phi

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Tell us you were here

Recent Posts

Farewell to a Familiar HPC Friend

May 27, 2020 By Rob Farber Leave a Comment

TechEnablement Blog Sunset or Sunrise?

February 12, 2020 By admin Leave a Comment

The cornerstone is laid – NVIDIA acquires ARM

September 13, 2020 By Rob Farber Leave a Comment

Third-Party Use Cases Illustrate the Success of CPU-based Visualization

April 14, 2018 By admin Leave a Comment

More Tutorials

Learn how to program IBM’s ‘Deep-Learning’ SyNAPSE chip

February 5, 2016 By Rob Farber Leave a Comment

Free Intermediate-Level Deep-Learning Course by Google

January 27, 2016 By Rob Farber Leave a Comment

Intel tutorial shows how to view OpenCL assembly code

January 25, 2016 By Rob Farber Leave a Comment

More Posts from this Category

Top Posts & Pages

  • SC15 - Accelerator Use in World’s Top Supercomputers
  • Learn how to program IBM's 'Deep-Learning' SyNAPSE chip
  • NVIDIA Tegra K1 Powered Shield Should Soon Be Available
  • OpenACC Adoption Continues to Gain Momentum in 2016
  • Rob Farber

Archives

© 2026 · techenablement.com