Managed memory greatly simplifies programming GPUs and Intel Xeon Phi coprocessors (when used in offload mode) because data can be utilized on either the host or the device without having to perform explicit device transfers. Instead the device(s) and host interact through the device driver to transparently migrate data as needed. As a result, application codes tend to be … [Read more...]
CreativeC GPU And Intel Xeon Phi Cluster For SC14 Class Runs Mobile In Van
Our all-day class at SC14 on Sunday November 16, “From ‘Hello World’ to Exascale Using x86, GPUs and Intel Xeon Phi Coprocessors” (tut106s1) received more than double our expected enrollment! Students will be able to run on both Intel Xeon Phi and GPU supercomputers at TACC via an Xsede allocation (thank you very much) and on a CreativeC supercomputer and visualization cluster … [Read more...]
Under $200 Intel Xeon Phi
For a limited time Intel is selling Intel® Xeon Phi™ Coprocessor 31S1P for under $200. This offer is designed for Software developers to cost-effectively purchase systems or clusters from OEMs to modernize their code for greater levels of performance. See one of the OEMs at this link, or Intel your rep for eligibility requirements. Additionally, as part of this developer … [Read more...]
Sparse matrix-vector multiplication: parallelization and vectorization
The chapter authors (Albert-Jan N. Yzelman, Dirk Roose, and Karl Meerbergen) note that, "Current hardware trends lead to an increasing width of vector units as well as to decreasing effective bandwidth-per-core. For sparse computations these two trends conflict.” For this reason they designed a usable and efficient data structure for vectorized sparse computations on … [Read more...]
Heterogeneous MPI Optimization With ITAC
This chapter focuses on the workload balance of MPI applications running in heterogeneous cluster environment consisting of Intel Xeon processors and Intel Xeon Phi coprocessors in a financial industry application that calculates Asian option payoffs. Three cases are considered: unbalanced symmetric MPI code, manual balancing with pre-calculated performances of the cluster … [Read more...]
Profiling Guided Optimization On Intel Xeon Phi
This chapter in High Performance Parallelism Pearls by Andrey Vladimirov focuses on the use of Intel VTune Amplifier XE reports to understand where to apply optimization on matrix transposition, a small and self-contained workload of great practical value. The optimization process applied to the code relies exclusively on programming in a high-level language plus utilization of … [Read more...]
Characterization And Optimization Methodology Applied To Stencil Computations
The chapter discuss characterization and optimization methodology applied to a 3D finite differences (3DFD) algorithm used to solve constant or variable density isotropic acoustic wave equation (Iso3DFD). From an unoptimized version to the most optimized, the authors achieved a six-fold performance improvement on Intel Xeon E5-2697v2 processors and a nearly thirty-fold … [Read more...]
Portable Performance with OpenCL On Intel Xeon Phi
This High Performance Parallelism Pearl show the potential for using the OpenCL™ standard parallel programming language to deliver portable performance on Intel Xeon Phi coprocessors, Xeon processors, and many-core devices such as GPUs from multiple vendors. This portable performance can be delivered from a single program without needing multiple versions of the code, an … [Read more...]
High Performance Ray Tracing With Embree On Intel Xeon Phi
Ray tracing is a technique for generating images of synthetic scenes. Because ray tracing simulates the physics of light transport in the real world, it can be used to achieve high quality and even photorealistic results. The chapter authors in High Performance Parallelism Pearls describe how the Intel Embree ray tracing kernel library can be used to achieve high performance … [Read more...]
Data Transfer Using The Intel COI Library
This short chapter gives an introduction to the Intel COI library and discusses the pros and cons of different data buffers as well as provides benchmarks on transfer latency and bandwidth between the host and the coprocessor. For any non-trivial applications, there is likely going to be a need to share data between the host and the coprocessor. These valuable information are … [Read more...]