The chapter authors discuss the hardware heterogeneity found in modern clusters and then analyze a typical Intel Xeon Phi coprocessor accelerated node on the Stampede cluster at TACC, with an eye towards how MPI is used in similar clusters, and the positioning an MPI task within the node. The performance through different communication pathways is highlighted using micro … [Read more...]
Intel Reports 3Q14 Record Quarterly Revenue of $14.6 Billion
Intel Corporation today reported third-quarter revenue of $14.6 billion, operating income of $4.5 billion, net income of $3.3 billion and EPS of $0.66. The company generated approximately $5.7 billion in cash from operations, paid dividends of $1.1 billion, and used $4.2 billion to repurchase 122 million shares of stock. "We are pleased by the progress the company is making," … [Read more...]
Remote Teaching Rooms Available At SC14
Faculty members who plan to attend the SC14 conference will have access to two dedicated rooms for remotely teaching their courses. The two facilities are rooms 256 and 257 in the convention center in New Orleans. The rooms will be available from 8 a.m. to 5 p.m. Tuesday, Nov. 18 through Thursday, Nov. 20 (Central Standard Time). Faculty who want to use the … [Read more...]
Concurrent Kernel Offloading On Intel Xeon Phi
Chapter 12 of High Performance Parallelism Pearls discusses optimizing performance when offloading concurrent kernels (e.g. task-parallelism) to the Intel Xeon Phi coprocessor. The authors state, "Our ultimate optimization target in this chapter is to improve the computational throughput of multiple small-scale workloads on the Intel Xeon Phi coprocessor by concurrent kernel … [Read more...]
Augmented Reality Company Magic Leap Bought by Google for $500M
The reports are that the highly secretive augmented reality company Magic Leap has been acquired by Google for $500M. The acquisition of Magic Leap signals the chocolate factory wishes to become the Hersey's chocolatier for the augmented reality industry and demonstrates the demand for augmented reality applications. TechEnablement is observing a movement towards … [Read more...]
Dynamic Load Balancing using OpenMP 4.0
Gilles Civario and Michael Lysaght from ICHEC show how to take advantage of the OpenMP 4.0 standard on Xeon and Intel Xeon Phi coprocessors to portably and efficiently maximize an N-body kernel on the entire available hardware. The chapter authors point out that the sample code can be used as a template applicable for countless of real live codes. By adapting this template to … [Read more...]
Free Colfax Intensive Intel Xeon Phi Training Slides
Colfax International is making the 280 page slide deck by Andrey Vladimirov and Vadim Karpusenko titled "Parallel Programming and Optimization with Intel Xeon Phi Coprocessors" available free to those who wish to register at this URL. This training is an intensive course for developers wishing to leverage the Intel MIC architecture. and increase their knowledge of multi-core … [Read more...]
OpenCL Included! Intel Integrated Native Developer Experience
Intel just released INDE. the Intel® Integrated Native Developer Experience cross-platform development suite that is claimed to provide a complete, consistent set of C++ and Java tools, libraries, and samples for environment setup, code creation, compilation, debugging, and analysis on Intel® architecture-based devices and select capabilities on ARM-based Android devices. The … [Read more...]
N-body Methods on Intel Xeon Phi Coprocessors
The chapter authors (Rio Yokota and Mustafa Abdul Jabbar) achieve roughly 1.5 TF/s single-precision performance when running an optimized direct N-body kernel on an Intel Xeon Phi coprocessor. This level of performance was achieved through the use of OpenMP, SIMD directives, and _mm512 intrinsics. The authors note the strong scalability of the execution was close to ideal, … [Read more...]
A Many-Core Implementation Of The Direct N-body Problem
Chapter 9 of High Performance Parallelism Pearls presents several optimizations that are usually necessary to obtain good performance on an Intel Xeon Phi coprocessor that include: introducing a softening factor, exploring the impact of single- vs. double-precision, Improving tililing, utilizing an SoA (Structure of Arrays) layout, generating code that does not maintain IEEE … [Read more...]